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VMMK-2203 0.9-11 ghz e-phemt wideband amplifer in wafer level package data sheet description avago technologies has combined its industry leading e-phemt technology with a revolutionary wafer level package (wlp). the VMMK-2203 is an easy-to-use gaas mmic amplifer that ofers excellent gain and noise fgure from 0.9 to 11 ghz. the input and output are matched to 50 so no external matching is needed. bias is supplied through a simple external choke and dc blocking network. the wafer level package is small and ultra thin, yet can be handled and placed with standard 0402 pick and place assembly. this product is easy to use since it requires only a single positive dc voltage for bias and no matching co - efcients are required for impedance matching to 50 systems. wlp 0402, 1mm x 0.5mm x 0.25 mm attention: observe precautions for handling electrostatic sensitive devices. esd machine model = 40v esd human body model = 450v refer to avago application note a004r: electrostatic discharge, damage and control. dy pin connections (top view) note: d = device code y = month code features ? 1 x 0.5 mm surface mount package ? ultrathin (0.25mm) ? gain block ? ultra-wide bandwidth ? 5v supply ? rohs6 + halogen free specifcations (6ghz, 5v, 25ma typ.) ? noise figure: 2.0db typical ? associated gain: 16.5db ? output ip3: +14dbm ? output p1db: +5dbm applications ? low noise and driver for cellular/pcs and wcdma base stations ? 2.4 ghz, 3.5ghz, 5-6ghz wlan and wimax note - book computer, access point and mobile wireless applications ? 802.16 & 802.20 bwa systems ? wll and mmds transceivers ? point-to-point radio ? uwb ? antennas dy output / vdd input amp input output / vdd
2 table 1. absolute maximum ratings [1] sym parameters/condition unit absolute max vd supply voltage (rf output) [2] v 8 id device current [2] ma 50 p in, max cw rf input power (rf input) [3] dbm +13 p diss total power dissipation mw 400 tch max channel temperature c 150 jc thermal resistance [4] c/w 107 notes 1. operation in excess of any of these conditions may result in permanent damage to this device. 2. bias is assumed dc quiescent conditions 3. with the dc (typical bias) and rf applied to the device at board temperature tb = 25c 4. thermal resistance is measured from junction to board using ir method table 2. dc and rf specifcations t a = 25c, frequency = 6 ghz, vd = 5v, z in = z out = 50 (unless otherwise specifed) sym parameters/condition unit minimum typ. maximum id device current ma 20.0 25 30.0 nf [1] noise figure db C 2 2.5 ga [1] associated gain db 15 16.5 18 oip3 [2,3] output 3rd order intercept dbm +14 C output p-1db [2] output power at 1db gain compression (pin = 0dbm) dbm +5 C irl [2] input return loss db C -11 C orl [2] output return loss db C -16 C notes: 1. measure data obtained using 300um g-s probe on production wafer 2. measure data obtained using 300um g-s-g probe on pcb substrate 3. oip3 test condition: f1 = 6.0ghz, f2 = 6.01ghz, pin = -20db
3 product consistency distribution charts at 6.0 ghz, vd = 5 v id @ 5v, mean=25ma, lsl=20ma, usl=30ma gain @ 6ghz, mean=16.5, lsl=15db, usl=18db nf @ 6ghz, mean=2db, usl=2.5db .02 .022 .024 .026 .028 .03 lsl usl 1.7 1.8 1.9 2 2.3 2.1 2.2 2.5 2.4 usl 15 16 17 18 lsl usl note: distribution data based on 500 part sample size from 3 lots during initial characterization. measurements were obtained using 300um g-s production wafer probe. future wafers allocated to this product may have nominal values anywhere between the upper and lower limits.
4 VMMK-2203 typical performance (t a = 25c, vdd = 5v, idd = 25ma, z in = z out = 50 unless noted) figure 1. small-signal gain [1] figure 3. input return loss [1] figure 5. output p-1db [1] figure 2. noise figure [1] figure 4. output return loss [1] figure 6. output ip3 [1] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 2. output ip3 data taken at pin= -20dbm 0 2 4 6 8 10 12 frequency (ghz) s21 (db) 0 1 2 3 0 2 4 6 8 10 12 frequency (ghz) nf (db) -20 -15 -10 -5 0 0 2 4 6 8 10 12 frequency (ghz) s11 (db) 0 2 4 6 8 10 0 2 4 6 8 10 12 frequency (ghz) p1db (dbm) -50 -40 -30 -20 -10 0 0 2 4 6 8 10 12 frequency (ghz) s22 (db) 10 12 14 16 18 20 0 2 4 6 8 10 12 frequency (ghz) oip3 (dbm) 10 12 14 16 18 20
5 VMMK-2203 typical performance (continue) (t a = 25c, vdd = 5v, idd = 25ma, z in = z out = 50 unless noted) figure 7. total current [1] figure 9. gain over vd [1] figure 11. input return loss over vdd [1] figure 8. noise figure over vd [1] figure 10. isolation over vd [1] figure 12. output return loss over vdd [1] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 0 5 10 15 20 25 30 0 1 2 3 4 5 6 vd (v) id (ma) 10 12 14 16 18 20 frequency (ghz) s21 (db) 5v 3v 5v 3v -20 -15 -10 -5 0 frequency (ghz) s11 (db) 0 1 2 3 4 0 2 4 6 8 10 12 frequency (ghz) nf (db) -50 -40 -30 -20 -10 0 0 2 4 6 8 10 12 frequency (ghz) s12 (db) -50 -40 -30 -20 -10 0 0 2 4 6 8 10 12 frequency (ghz) s22 (db) 0 2 4 6 8 10 12 0 2 4 6 8 10 12 5v 3v 5v 3v 5v 3v
6 VMMK-2203 typical performance (continue) (t a = 25c, z in = z out = 50 unless noted) figure 13. output p-1db over vdd [1] figure 15. gain over temp [3] figure 17. output p1db over temp [3] figure 14. output ip3 over vdd [1,2] figure 16. noise figure over temp [3] figure 18. output ip3 over temp [2,3] notes: 1. data taken on a g-s-g probe substrate fully de-embedded to the reference plane of the package 2. output ip3 data taken at pin=-15dbm 3. over temp data taken on a test fxture (figure 20) without de-embedding -10 -5 0 5 10 0 2 4 6 8 10 12 frequency (ghz) p1db (dbm) op1db_5v op1db_3v 10 12 14 16 18 20 0 2 4 6 8 10 12 frequency (ghz) s21 (db) 0 1 2 3 4 5 0 2 4 6 8 10 12 frequency (ghz) nf (db) 25 c 85 c -40 c 0 5 10 15 20 0 2 4 6 8 10 12 frequency (ghz) oip3 (dbm) 0 3 6 9 12 15 0 2 4 6 8 10 12 frequency (ghz) p1db (dbm) 0 5 10 15 20 25 0 2 4 6 8 10 12 frequency (ghz) oip3 (dbm) oip3_5v oip3_3v 25 c 85 c -40 c 25 c 85 c -40 c 25c 85c -40c
7 typical scattering parameters (data obtained using 300um g-s-g pcb substrate, losses calibrated out to the package reference plane) t a = 25 c , v dd = 5v, i dq = 25ma, z in = z out = 50 freq ghz s11 s21 s12 s22 db mag phase db mag phase db mag phase db mag phase 0.1 -0.623 0.931 -17.303 15.410 5.895 24.706 -43.098 0.007 58.201 -14.226 0.194 -60.924 0.2 -1.806 0.812 -30.763 16.296 6.528 11.177 -39.251 0.011 49.500 -18.666 0.117 -67.718 0.3 -3.217 0.691 -40.107 16.744 6.874 3.676 -37.202 0.014 38.074 -21.230 0.087 -71.757 0.4 -4.789 0.576 -42.585 16.937 7.028 0.281 -36.138 0.016 30.992 -25.224 0.055 -69.531 0.5 -6.014 0.500 -45.376 17.138 7.193 -4.222 -35.494 0.017 23.868 -27.013 0.045 -72.073 0.9 -9.520 0.334 -46.030 17.440 7.447 -19.422 -34.943 0.018 10.054 -32.841 0.023 -83.598 1 -10.053 0.314 -45.287 17.468 7.471 -22.849 -34.846 0.018 8.211 -34.657 0.019 -82.547 2 -11.859 0.255 -36.749 17.573 7.562 -54.672 -34.992 0.018 -7.465 -41.210 0.009 161.055 3 -11.242 0.274 -40.341 17.447 7.453 -85.386 -35.810 0.016 -16.631 -31.341 0.027 84.468 4 -10.554 0.297 -54.521 17.046 7.117 -115.626 -36.954 0.014 -23.677 -23.890 0.064 49.757 5 -10.446 0.300 -70.762 16.351 6.570 -144.946 -38.862 0.011 -26.344 -18.666 0.117 27.200 6 -10.989 0.282 -88.565 15.548 5.989 -172.420 -40.724 0.009 -25.092 -15.376 0.170 10.065 7 -11.965 0.252 -105.725 14.741 5.458 161.832 -42.158 0.008 -15.494 -13.046 0.223 -5.275 8 -13.267 0.217 -123.379 14.054 5.043 137.412 -43.098 0.007 -4.492 -11.179 0.276 -18.954 9 -14.919 0.180 -142.510 13.539 4.753 113.475 -42.853 0.007 8.295 -9.538 0.334 -31.497 10 -16.701 0.146 -166.823 13.159 4.550 89.158 -42.384 0.008 19.326 -8.011 0.398 -43.146 11 -17.972 0.126 163.087 12.879 4.405 63.721 -40.724 0.009 23.652 -6.616 0.467 -55.112 12 -17.781 0.129 128.897 12.543 4.238 36.160 -39.332 0.011 26.908 -5.338 0.541 -68.500 13 -16.496 0.150 97.602 11.875 3.924 6.410 -37.924 0.013 22.544 -4.465 0.598 -83.481 14 -14.943 0.179 72.431 10.617 3.395 -24.069 -37.788 0.013 14.404 -4.124 0.622 -98.826 15 -13.731 0.206 54.358 8.757 2.741 -53.104 -37.589 0.013 8.991 -4.278 0.611 -112.509 16 -12.597 0.235 40.489 6.512 2.116 -78.994 -37.856 0.013 6.710 -4.834 0.573 -123.438 17 -11.805 0.257 29.853 4.131 1.609 -101.974 -38.273 0.012 7.867 -5.430 0.535 -132.619 18 -10.906 0.285 20.369 1.789 1.229 -122.236 -38.416 0.012 4.077 -5.883 0.508 -139.697 19 -10.128 0.312 12.841 -0.460 0.948 -140.763 -38.862 0.011 3.017 -6.200 0.490 -145.124 20 -9.549 0.333 5.210 -2.569 0.744 -158.032 -39.412 0.011 -1.898 -6.375 0.480 -150.506
8 figure 19. usage of the VMMK-2203 figure 20. evaluation/test board (available to qualifed customer request) VMMK-2203 application and usage (please always refer to the latest application note an5378 in website) biasing and operation the VMMK-2203 is biased with a positive supply connected to the output pin through an external user supplied bias-tee as shown in figure 19. the recommended supply voltage is between 3 and 5v. the corresponding drain currents are approximately 15 and 25 ma. biasing the device at 5v results in higher gain, lower noise fgure, higher ip3 and p1db. in a typical application, the bias-tee can be constructed using lumped elements. the value of the output inductor can have a major efect on both low and high frequency operation. the demo board uses an 8.2 nh inductor that has self resonant frequency higher than the maximum desired frequency of operation. amp input vdd output output pad ground pad input pad 50 ohm line 50 ohm line 100 pf 0.1 uf 8.2 nh 100 pf 100 pf size: 1.1 mm x 0.6 mm (0402 component) at frequencies higher than 6 ghz, it may be advanta - geous to use a quarter-wave long microstrip line to act as a high impedance at the desired frequency of operation. this technique proves a good solution but only over rela - tively narrow bandwidths. another approach for using the VMMK-2203 in broadband is to put in series two diferent value inductors with the smaller value inductor placed closest to the device and favoring the higher fre - quencies. the larger value inductor will then ofer better low frequency performance by not loading the output of the device. the parallel combination of the 100pf and 0.1uf capacitors provides a low impedance in the band of operation and at lower frequencies. they should be placed as close as possible to the inductor. the low frequency bypass provides good rejection of power supply noise and also provides a low impedance termination for third order low frequency mixing products that will be generated when multiple in-band signals are injected into any amplifer. refer the absolute maximum ratings table for allowed dc and thermal conditions. s parameter measurements the s-parameters are measured on a .016 inch thick ro4003 printed circuit test board, using g-s-g (ground signal ground) probes. coplanar waveguide is used to provide a smooth transition from the probes to the device under test. the presence of the ground plane on top of the test board results in excellent grounding at the device under test. a combination of solt (short - open - load - thru) and trl (thru - refect - line) calibration tech - niques are used to correct for the efects of the test board, resulting in accurate device s-parameters. the reference plane for the s parameters is at the edge of the package. the product consistency distribution charts shown on page 2 represent data taken by the production wafer probe station using a 300um g-s wafer probe. the ground-signal probing that is used in production allows the device to be probed directly at the device with minimal common lead inductance to ground. therefore there will be a slight dif - ference in the nominal gain obtained at the test frequency using the 300um g-s wafer probe versus the 300um g-s-g printed circuit board substrate method.
9 outline drawing suggested pcb material and land pattern notes: 1. 0.010 rogers ro4350 recommended smt attachment the vmmk packaged devices are compatible with high volume surface mount pcb assembly processes. manual assembly for prototypes 1. follow esd precautions while handling packages. 2. handling should be along the edges with tweezers or from topside if using a vacuum collet. 3. recommended attachment is solder paste. please see recommended solder refow profle. conductive epoxy is not recommended. hand soldering is not recommended. 4. apply solder paste using either a stencil printer or dot placement. the volume of solder paste will be dependent on pcb and component layout and should be controlled to ensure consistent mechanical and electrical performance. excessive solder will degrade rf performance. 5. follow solder paste and vendors recommendations when developing a solder refow profle. a standard profle will have a steady ramp up from room temperature to the pre-heat temp to avoid damage due to thermal shock. 6. packages have been qualifed to withstand a peak temperature of 260 c for 20 to 40 sec. verify that the profle will not expose device beyond these limits. 7. clean of fux per vendors recommendations. 8. clean the module with acetone. rinse with alcohol. allow the module to dry before testing. 3 figure 5. recommended pcb layout for vmmk devices 1.2 (0.048) 0.100 (0.004) 0.500 (0.020) 0.500 (0.020) 0.400 (0.016) 0.100 (0.004) 0.254 dia pth (0.010) 4pl 0.400 dia (0.016) 4pl 0.200 (0.008) 0.381 (0.015) 2pl 0.200 (0.008) part of input circuit part of output circuit 0.076 max (0.003) 2pl - see discussion solder mask 0.7 (0.028) printed circuit board material and vias the pcb board material stack used to qualify the device consists of 40 mil thickness fr4 core material with one ounce copper for both top and bottom metal. soldering onto materials with greater thermal expansion than fr5 or high tg fr4 should be avoided. board materials with high cte, such as tefon, may lead to damage of the base of the gaas package which contains the device circuitry or may lead to damage of the cap of the gaas package which defnes the air cavity, or may lead to damaging both. low loss microwave materials such as ro4003 and ro4350 have ctes similar to fr4 type material and should be acceptable pcb materials. recommended pcb foot p rint and grounding establishing a proper ground for either the source leads of the vmmk-1xxx series or the common leads of the vmmk-2xxx and -3xxx series is paramount. the rec- ommended printed circuit board via pattern is shown in figure 5. this is a non-solder mask defned footprint (nsmd). the outline of the solder mask that borders the device is shown by the area indicated in green. the recommended footprint does not require any plated through holes under the device. modeling and tests indicate that placing vias adjacent to (within .003) and on either side of the device as shown in figure 5 provides good grounding for the vmmk-2xxx and vmmk-3xxx series devices when mounted on .010 thickness ro4350 printed circuit board material. this technique also applies when using the vmmk-1xxx discrete fets at frequencies greater than 10 ghz. when using the vmmk-1xxx fets at low frequencies, some amount of source inductance may actually be required. in this case, the vias may be placed further away from the device to enhance stability. consult individual application notes for more information. due to the proximity of the vias to the edge of the vmmk device (less than .003 ), it is recommended that the vias be flled to minimize wicking of the solder from under the vmmk device. in addition, since the edge of the vias is slightly outside of the solder mask area, the vias should be flled. vias can be flled with a conductive via fll material or a non-conductive via fll material. possible non-conductive via fll materials include: san-ei kagaku php-900 ir6 taiyo ink hb 12000 db4 dielectric prepreg material solder mask material as a general rule, if a via is within .004 (100u) of the edge of the soldermask but not under the device, then the via should be flled. any via which is covered by the solder mask and is beyond .004 (100u) of the solder mask edge can be uncapped and unflled as it is not at risk of wicking away solder from the device. if for any reason it is required to include a via or vias under a vmmk device, then the vias should be flled and capped. a capped via is a plated over flled via. if a flled but uncapped via is placed under the device, there will not be enough solderable surface area for device attach- ment. if an unflled and uncapped via is placed directly under the ground pad, then the liquid solder will fow into the open via hole during the refow process and deplete the solder volume to varying degrees from under the ground pad. depletion of the solder volume due to unflled vias may lead to a weak solder joint, poor grounding of the device, and/or stresses compromising the structural integrity of the package. the recommended footprint provides a solder joint that meets jedec standards for die shear, and provides sufcient adhesion of the ground lead such that the mechanical integrity of the package remains intact should any minor deformation of the board occur due to thermal shock. pin one indicator 0.125 0.125 output pad 0.470 input pad 0.160 0.160 0.390 1.004 min, 1.085 max 0.500 min, 0.585 max ground pad notes: solderable area of the device shown in yellow. dimensions in mm. tolerance 0.015 mm
10 ordering information part number devices per container container VMMK-2203-blkg 100 antistatic bag VMMK-2203-tr1g 5000 7 reel package dimension outline reel orientation device orientation top view end view ? dy ? dy ? dy ? dy 8 mm 4 mm note: ?d? = device code ?y? = month code u s e r f e e d d i r e c ti o n not e: all dimensions ar e in mm a e d d ie dimension: d im range unit d 1.004 - 1.085 mm e 0.500 - 0.585 mm a 0.225 - 0.275 mm user feed direction carrier tape reel
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2014 avago technologies. all rights reserved. av02-2001en - december 16, 2014 notice: 1. 10 sprocket hole pitch cumulative tolerance is 0.1mm. 2. pocket position relative to sprocket hole measured as true position of pocket not pocket hole. 3. ao & bo measured on a place 0.3mm above the bottom of the pocket to top surface of the carrier. 4. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 5. carrier camber shall be not than 1m per 100mm through a length of 250mm. unit: mm symbol spec. k1 C po 4.00.10 p1 4.00.10 p2 2.00.05 do 1.550.05 d1 0.50.05 e 1.750.10 f 3.500.05 10po 40.00.10 w 8.00.20 t 0.200.02 note: 2 p2 note: 1 po do b b note: 2 e f w a a p1 d1 r0.1 ao 5 (max) scale 5:1 aa section ao = 0.730.05 mm bo = 1.260.05 mm ko = 0.35 +0.05 mm +0 scale 5:1 bb section 5 (max) bo ko t tape dimensions

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